The present application relates to semiconductor device fabrication, and more particularly to the fabrication of dense semiconductor features including semiconductor fins/nanowires using epitaxy growth.
With the continuing trend towards miniaturization of integrated circuits (ICs), there is a need for transistors with increasingly smaller dimensions. Fin field effect transistor (FinFET) and nanowire FET architectures are becoming more prevalent as device size continues to shrink.
Making dense features such as semiconductor fins or nanowires for FinFETs or nanowire FETs is challenging. Photolithography is reaching its limit. With current immersion lithographic techniques using 193 nm light, a minimum pitch size between features is about 80 nm. Side image transfer (SIT) and direct self-assembly (DSA) have been developed to create features with widths substantially smaller than the minimum size allowed by a given lithographic process. However, SIT and DSA processes are limited in the density of structures that they can provide. Therefore, there remains a need for the fabrication of dense features for FinFETs or nanowire FETs.